1. Field of the Invention
The invention generally relates to enhancing the parasitic bipolar turn-on which is formed via the junctions of the field effect transistor. This includes a reduced trigger/turn-on voltage region (P+ zener-like implant beneath the junction) below the drain region that comprises an undoped region of the pure wafer substrate.
2. Description of the Related Art
Electrostatic charges are a constant threat to modern electronics. Therefore, electrostatic discharge protection (ESD) devices are an important component of the protection circuitry provided in today's electronic devices. As the technologies scale and the ESD protection requirements stay constant, effective ESD protection will become even more difficult in the future. This drives the need for continuous improvement and innovation in this area. To be as effective as possible, low trigger voltage ESD protection devices such as N-type field effect transistors (NFETs) are used because such devices provide effective protection (the parasitic lateral NPN beneath NFET turns on during an ESD event), decrease the area of the chip consumed, and reduce the capacitive loading of the ESD devices. An improved parasitic NPN transistor that has a low trigger voltage and low leakage and can be effectively used as an ESD protection device is presented below.